In a typical system, a number of sources can generate inter-lane skew, the last of which is the receiver logic itself. Because of the nondeterministic phase relationship between the parallel PMA RXCLK and RXUSRCLK in each tile, there is potential for up to 40 UI or one internal data word of skew to be introduced when crossing between the PMA and PCS clock boundaries in the Virtex-4 GT11 MGT.
Fortunately, the GT11 has the ability to phase align the PMA RXCLK and RXUSRCLK, which eliminates this additional source of skew. For channel bonded applications, please follow the guidelines in the Virtex-4 RocketIO Transceiver Users Guide on page 228:
This additional 40 UI of skew should be included when calculating the skew tolerance of any channel-bonded system. If channel bond sequences are far enough apart that two will not appear in the elastic buffer at the same time, increasing CHAN_BOND_LIMIT can be a simple alternative.