We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 30956

Virtex-4 Configuration - The IEEE 1532 programming flow is not programming the device


The current ".isc" files and BSDL files from the 10.1 sp1 design tools (and earlier) will not program a Virtex-4 device in 1532 mode.


There are two issues that will need to be corrected if the 10.1.02 (or earlier) version of the tools is being used to enable the 1532 BSDL file format. The following items need to be taken into consideration:

1. The ".isc" files need to have the following line added to the front of the file:


Next, one of the following lines will need to be removed in the first section of the file:

00000004, 00000004, 00000004, 00000004, 00000004, 00000004,

2. The 1532 BSDL file will need to have the following command

Current command in the Virtex-4 files:

"ISC_DISABLE (1111010111)," &

Actual command, which is the same as in Virtex-5:

"ISC_DISABLE (1111010110)";

This has been resolved in 10.1.03.

Also, there are general requirements in regards to the startup clock setting: the STARTUP CLOCK must be set to CCLK. This is performed in the BitGen tool with the -g StartUpClk:CClk. If the ISE GUI is being used, the "Generate Programming File" properties will allow the CCLK to be selected in the Startup Options menu.

AR# 30956
Date 12/15/2012
Status Active
Type General Article
Page Bookmarked