When I attempt to export a design as an FSL PCore for EDK, the following error message occurs:
"Error running xledkpostgen
Error using ==> feval
Error: <a href="error:C:\Xilinx\10.1\DSP_Tools\sysgen\plugins\compilation\EDK Export Tool\xledkpostgen.m,734,8">File: xledkpostgen.m Line: 734 Column: 8</a>
Arguments to IMPORT must either end with ".*"
or else specify a fully qualified class name: "com.xilinx.sysgen.netlister.EDKPCoreBuilder" fails this test."
This is a known issue in System Generator for DSP 10.1 and 10.1.01.
You can use the PLB PCORE output as a work-around. PLB is the preferred bus for EDK peripherals.
This issue has been fixed in System Generator for DSP 10.1 Service Pack 2, and will allow you to generate an FSL PCORE.