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AR# 30970

LogiCORE SPI-4.2 (POS-PHY L4) Lite v4.3 - Release Notes and Known Issues for 10.1 IP Update 2 (10.1_IP2)

Description

These Release Notes and Known Issues are for the SPI-4.2 (POS-PHY L4) Lite v4.3, released in 10.1 IP Update 2, and they contain the following information: 

 

- New Features 

- Bug Fixes 

- General Information 

- Known Issues 

 

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at: 

http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf

Solution

New Features in v4.3  

 

- ISE 10.1 design tools support added 

- Synopsys VCS simulator Verilog support added 

 

Bug Fixes in V4.3 

 

None 

 

General Information 

 

(Xilinx Answer 20430) What is the power consumption of SPI-4.2 Lite Core?  

(Xilinx Answer 20017) Which I/O Standards are supported for SPI-4.2 Core?  

Multiple Cores: If you are using multiple SPI-4.2 Cores in a single device, see the "Multiple Core Instantiation" section under the "Special Design Consideration" chapter of the SPI-4.2 Lite User Guide. It is important to generate multiple cores with unique component names for each instance regardless of core configuration. 

 

Known Issues in v4.3  

 

-In the CORE Generator GUI, the version information might indicate that the core is v4.3 Rev1. "Rev 1" does not mean that this is a patch release; please ignore "Rev 1". 

 

Constraints and Implementation Issues 

 

(Xilinx Answer 22009) When implementing an SPI-4.2 Lite design through NGDBuild, several "INFO" and "WARNING" messages appear 

(Xilinx Answer 21998) When implementing an SPI-4.2 Lite design through MAP, several "WARNING" messages appear  

(Xilinx Answer 21999) When implementing an SPI-4.2 Lite design through BitGen, several "WARNING" messages appear  

(Xilinx Answer 22011) There are missing example constraints in the UCF file  

(Xilinx Answer 19999) "ERROR:BitGen:169 - This design contains one or more evaluation cores for which bitstream generation is not supported" 

 

General Simulation Issues 

 

(Xilinx Answer 21319) TDat Error: Data mismatch error in timing simulation 

(Xilinx Answer 22001) Design example results in warnings for source segmenting packets  

(Xilinx Answer 21350) Demo testbench results in RDat Protocol violation warnings  

(Xilinx Answer 21322) Timing simulation errors: SETUP, HOLD, RECOVERY violations  

(Xilinx Answer 22026) Simulating SPI-4.2 Lite design results in "Error: /X_ODDR HOLD Low VIOLATION ON D1 WITH RESPECT TO C;" 

 

Hardware Issues 

 

(Xilinx Answer 32023) Virtex-4 or Virtex-5 core might fail in hardware  

 

(Xilinx Answer 20022) When fixed static alignment is used, it is necessary to determine the best IOBDELAY (ISERDES) value or the best DCM setting (PHASE SHIFT) to ensure that the target system contains the maximum system margin and performs across voltage, temperature, and process (multiple chips) variations.  

 

SPI- 4.2 (PL4) Lite v4.2 KNOWN ISSUES 

 

- The SPI-4.2 Lite v4.2 Core is now obsolete. Please upgrade to the latest version of the core.  

For information on existing SPI-4.2 Lite v4.2 issues, see (Xilinx Answer 24556)

 

SPI- 4.2 (PL4) Lite v4.1 KNOWN ISSUES 

 

- The SPI-4.2 Lite v4.1 Core is now obsolete. Please upgrade to the latest version of the core.  

For information on existing SPI-4.2 Lite v4.1 issues, see (Xilinx Answer 23488)

 

SPI- 4.2 (PL4) Lite v3.1 KNOWN ISSUES 

 

- The SPI-4.2 Lite v3.1 Core is now obsolete. Please upgrade to the latest version of the core.  

For information on existing SPI-4.2 Lite v3.1 issues, see (Xilinx Answer 22390)

 

Revision History 

 

06/19/2008 - Initial Release 

01/06/2009 - Added AR 32023 to Hardware Issues

AR# 30970
Date Created 06/18/2008
Last Updated 05/22/2014
Status Archive
Type General Article