We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 30988

10.1 Virtex-5 PAR 10.1 - Dedicated routing not used when clock input uses IDELAY to drive BUFG


Keywords: dedicated, routing, IDELAY, BUFG

When using an IDELAY on my Global Clock Capable input pin, the router is not using the dedicated routing to the BUFG. How can I set up the tools to use the dedicated routing between IODELAY and the BUFG?


This routing problem can be worked around by manually routing the BUFG connection in FPGA Editor and then creating a Directed Routing constraint to force the same routing to be used during subsequent automatic routing of the design. FPGA Editor creates a UCF constraint that controls the routing for that net in future revisions.

For more information on how to route using FPGA editor, and how to export directed routing constraints, refer to FPGA Editor Help section, and the Constraints Guide using Directed Routing constraint.

Link to the Constraints Guide:

This problem is currently being investigated for a fix in a future ISE revision.

AR# 30988
Date 06/16/2008
Status Active
Type General Article