UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 31069

10.1.01 System Generator for DSP - When I use asymmetrical reloadable coefficients in my FIR Compiler the results are incorrect

Description

My design is using the FIR Compiler v3.2 with reloadable coefficients. I specify my coefficients to be asymmetrical. However, when I use the reload port to load a new set of coefficients, the FIR Compiler appears to treat my coefficients as symmetrical and only uses the first half of the coefficients that I have loaded.

Solution

This is due to a known issue in System Generator for DSP 10.1.01. This version of the tool does not properly simulate asymmetrical coefficients for the reload feature. This issue does not affect hardware or HDL simulation, only the simulation behavior in System Generator. 

 

This issue is resolved in System Generator for DSP 10.1 Service Pack 2.

AR# 31069
Date Created 05/28/2008
Last Updated 05/22/2014
Status Archive
Type General Article