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AR# 31078

HW - Why can T and non-T version I/O standards not be placed in the same bank on ISE 10.1 SP1 or later versions?

Description

Why can T and non-T version I/O standards not be placed in the same bank on ISE 10.1 SP1 or later versions?

Solution

HSTL/SSTL_DCI and its corresponding Tri-state (T) version I/O standard cannot be placed in the same bank, starting in ISE 10.1 sp1.

This change in the software is the result of the fact that placing certain combinations of HSTL/SSTL_DCI IO standards and their corresponding Tri-state (T) versions in the same bank might not meet the Signal Integrity (SI) requirement specified by the standard, and the increase of software complicity in order to accommodate all combinations of HSTL/SSTL_DCI IO standards and their corresponding Tri-state (T) versions is not possible with the current software algorithm.

Thus, beginning in ISE 10.1 sp1, Xilinx has chosen not to allow placing HSTL/SSTL_DCI IO standards and their corresponding Tri-state (T) versions in the same bank.

For users who have a proven design with HSTL/SSTL_DCI IO standards and their corresponding Tri-state (T) versions placed in the same bank, and use 10.1 or older versions, their designs might be fine, but staying with the original ISE version (ISE 10.1 or earlier) is required.

For designs that have to be compiled with ISE 10.1 sp1 or later version, a work-around for designs using HSTL/SSTL_DCI as input only is to change the HSTL/SSTL_DCI to its corresponding T version and have the tri-stated enable tie-off by connecting it to VCC, making sure to add attribute constraint "S" to the tri-state enable net in the UCF file (for example, NET "Tri-state_net_name" S).

NOTE: HSTL/SSTL_DCI I/O and its Differential version is treated as same I/O standard in terms of DCI banking compatibility.

AR# 31078
Date Created 05/29/2008
Last Updated 12/15/2012
Status Active
Type General Article