The Spartan-3 Generation DDR/DDR2 SDRAM MIG designs include a tap delay circuit within the physical layer; see (Xilinx XAPP454): "DDR2 SDRAM Interface for Spartan-3 Generation FPGAs" for details:
Proper tap delay implementation requires the circuit logic to be placed in one column. To force the implementation tools to always place the circuit in one column, MIG v2.2 sets the XIL_PAR_ALIGN_USER_RPMs environment variable. This is set in the ise_flow.bat script file located in the "par" directory of the generated MIG output.
Proper placement of the tap_dly circuit in one column can also be implemented with RLOC_ORIGIN constraints. This method is recommended if the environment variable causes issues with other parts of the design or if the UCF is being used with an EDK/MPMC design.
This answer record describes how to compute the correct RLOC_ORIGIN constraints and how to verify the correct placement of the tap_dly circuit using FPGA Editor.
Note: MIG v2.3 sets the RLOC_ORIGIN constraints rather than using the XIL_PAR_ALIGN_USER_RPMS environment variable.
Top Bank SelectionThe MIG output UCF includes an AREA_GROUP constraint on cal_ctl. The first value in the RANGE of this constraint is the value in the added RLOC_ORIGIN constraint. Here is an example AREA_GROUP from an MIG output UCF:
The MIG output UCF includes an AREA_GROUP constraint on cal_ctl. To calculate the RLOC_ORIGIN constraint, take the first value in the AREA_GROUP RANGE and add 10 to the X coordinate. Here is an example AREA_GROUP from an MIG output UCF:
AREA_GROUP "cal_ctl" RANGE = SLICE_X74Y4:SLICE_X85Y17;
The first value in the range is X74Y4. The new RLOC_ORIGIN value is X84Y4 since 10 is added to the X coordinate. The syntax for the new constraint to be added to the UCF file is:
INST "infrastructure_top0/cal_top0/tap_dly0/l0" RLOC_ORIGIN = X84Y4;
Verification of Tap Delay Circuit Placement
To verify placement of the tap_dly circuit, follow these steps:
1. Open the Post-PAR design.ncd and design.pcf files in FPGA Editor.
2. Select "Routed Nets" from the List window located at the top left-hand side. This shows all the routed net names of the design.
3. Enter "*tap_dly*/tap*" in the Name Filter window to select the tap_dly chain.
4. Select all the nets displayed, and click the Apply button on the right-hand side of the Name Filter window.
5. Zoom into the area in the Array window where the selected routes are highlighted.
If properly constrained, the logic will be located in a single column in four sequential CLBs. This will indicate the RLOC_ORIGIN is correct.
The following screen capture shows an example of the correct placement of the tap_dly circuits:
Note: The hierarchy structure and the naming convention shown above refer to the MIG generated design. Any change in design hierarchy and the naming convention should be taken into account.