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AR# 31110

ChipScope Pro - Instantiating VIO/ILA/ATC2 ChipScope Core results in "ERROR:NgdBuild:76"

Description

When I instantiate a VIO/ILA/ATC2 ChipScope core in my design and implement, an error occurs similar to the following at the NGDBuild stage:

"ERROR:NgdBuild:76 - File "<file_path>/vio.ngc" cannot be merged into block "vio" (TYPE="vio") because one or morepins on the block, including pin "sync_out", were not found in the file."

How can I work around this error?

Solution

Signal bit-widths for ChipScope cores must be declared as vectors. For example, the signal "sync_out" should be declared as "wire [0:0] sync_out". Also, in the instantiation template for the VIO core, this convention must be used. The "vio.v" file generated from CORE Generator shows this in the module declaration, following this format should work around this error. If they are declared as just a std_logic or wire, "ERROR:NgdBuild:76" will occur at the Translate stage of implementation. This is because the core instantiation will not match up with the netlist.

For example, a one bit port "sync_out" would be declared as follows:

input [0:0] sync_out

or

sync_out : in std_logic_vector(0 downto 0);

AR# 31110
Date Created 06/05/2008
Last Updated 01/02/2013
Status Active
Type General Article
Tools
  • ChipScope Pro