Why, when 8 bits is selected for the soft input data width and the extrinsic data, does the core use three BUFGs and thus reduces the performance of the core?
If the core selects 6 bits for the soft input/extrinsic data width a performance of ~205 MHz in a Virtex-5 xc5vlx110-ff676-1 can be expected.
However, if 8 bits is selected, the performance drops off to ~164 MHz. This results from the fact that when the netlist is generated, three BUFGs are used to reduce the fan out, which affects the performance.
If you have a requirement for a higher performance than 164 MHz, please open a webcase. Include the following:
Please see (Xilinx Answer 29447) for a detailed list of LogiCORE 802.16E Convolutional Turbo Code (CTC) Decoder Release Notes and Known Issues.