AR# 31144


LogiCORE FIFO Generator v4.x - Differences between FIFO v4.x cores and v3.x (and prior) cores


The FIFO Generator v4.x (for example, v4.3) cores have some resource usage and behavioral differences when compared to v3.x or older cores.


Resource Usage Differences


1. The LUT count is either the same or less in FIFO Generator v4.x

2. Additional register (detailed above) are from:

a. adding 1 copy of Full flag for internal core use to reduce fanout

b. adding 1 copy of Empty flag for internal core use to reduce fanout

c. modifications to the write and read reset synchronization logic (only for asynchronous resets). This is to address the

issue in v3.3 where the full flags are asserted at the same time as empty even after the reset signal is de-asserted


Reset Behavior Differences

1. Behavior of asynchronous resets with Full Flag Reset Value = 1 has changed:

2. In FIFO Generator v4.2, added asynchronous reset with Full Flag Reset Value = 0. This configuration requires a reset pulse of 4 clk cycles, and the FIFO is ready for operation immediately after the reset is deasserted.

AR# 31144
Date 12/15/2012
Status Active
Type General Article
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