We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 31147

10.1 Constraints System - Constraints propagated through DCM CLK2X port are not phase-shifted correctly


I constrained the input of my DCM at the input side, CLKIN_DIVIDE_BY_2 is set to TRUE, and I gave the DCM a fixed PHASE_SHIFT. The propagated constraint generated for the CLK2X by the constraints system does not take into account that the frequency is doubled; therefore, the phase shift is only half what it should be.


There are two ways to work around this issue. The first is to manually constrain the DCM output, giving the proper phase shift for each output of the DCM. The second is to set the environment variable to XIL_NGDBUILD_CS = 1.

See (Xilinx Answer 11630) for more information on setting environment variables.

AR# 31147
Date 12/15/2012
Status Active
Type General Article
Page Bookmarked