My design is failing to route successfully even though the resource utilization is not very high. While examining the MAP report (.map), I noticed that the global clock region allocation was not allocating enough clock regions for my largest clock domains. Is there any way to control this behavior other than to manually constrain all clock domains?
A problem has been seen with the global clock placer, where for some designs, the largest clock domains are not allocated enough clock regions. As a result, the design can either fail to place successfully, or the quality of the placement will be poor, leading to routing or timing problems.
A short-term solution has been provided in ISE 10.1sp3 under environment variable control. A more comprehensive solution will be provided in ISE 11.1.
There are two options for the ISE 10.1sp3 solution using one of the following environment variables:
1. XIL_PAR_CLKPH2_MAXIMIZE - When this variable is set to "1", the clock placer will automatically calculate how many of the highest fanout clock domains should be given priority for clock region allocation.
setenv XIL_PAR_CLKPH2_MAXIMIZE 1
2. XIL_PAR_CLKPH2_EXPAND_HIGHFANOUT_CLOCK - When this variable is set to an integer "N", the clock placer will give the N largest clock domains priority for clock region allocation. For example, you might decide that your three largest clock domains are large enough to require access to most of the devices' clock regions.
setenv XIL_PAR_CLKPH2_EXPAND_HIGHFANOUT_CLOCK 3
For general information about setting ISE environment variables, see (Xilinx Answer 11630).