The word "type" is used in the downstream port testbench file pci_exp_userap_com.v. This is a keyword in System Verilog and causes problems during compilation.
To work around this issue, perform a search and replace on "type", renaming it something else (for example, "frame_type").
This problem will be corrected in a future release.
06/18/2008 - Added BP v1.8
06/12/2008 - Initial Release