v1.7.1, v1.6.1, v1.5.2, v1.5.1, v1.5, v1.4, v1.3, v1.2, v1.1 Known Issues
In the CORE Generator GUI, there is an option to set the Slot Clock Configuration bit in the Link Status register. This bit is not being set even if the box is checked.
To work around this problem for hardware implementation, add the following in the UCF file:
INST "ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep" LINKSTATUSSLOTCLOCKCONFIG = "TRUE";
For simulation, open the simulation model generated by CORE Generator. Search for "LINKSTATUSSLOTCLOCKCONFIG" and change it to "TRUE".
Fixed in v1.9, which will be available in 10.1sp3 IP Update 3.
09/10/2008 - Updated with fix information.
06/12/2008 - Initial Release.