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AR# 31208

10.1 EDK, MPMC v4.00.a - Spartan-3 BSB designs have difficulty meeting timing

Description

Spartan-3 BSB designs have difficulty meeting timing, such as the Spartan-3A DSP 1800 board. How do I resolve this issue?

Solution

In the generated UCF from BSB, the MPMC section does not have a correct U_SET value set. 

 

For example, the initial UCF might contain the following: 

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0" RLOC=X0Y6; 

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0" U_SET = "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly*/l0"; 

... 

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[0].r" RLOC=X0Y6; 

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap 

1[0].r" U_SET = "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0"; 

 

The correct UCF should be: 

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0" RLOC=X0Y6; 

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0" U_SET = "delay_calibration_chain"; 

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[0].r" RLOC=X0Y6; 

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[0].r" U_SET = "delay_calibration_chain"; 

 

Fixing this ensures that LUT and FF for the tap delay logic in the MIG PHY are in the same slice, making timing results more predictable. 

 

This issue is fixed starting with new designs generated from BSB using EDK 10.1, Service Pack 2.

AR# 31208
Date Created 06/18/2008
Last Updated 05/21/2014
Status Archive
Type General Article