AR# 31216


10.1.02 System Generator for DSP - Release Notes, README, and Known Issues List


Keywords: MATLAB, Simulink, errata, KI, SysGen, 10.1.02

This Answer Record contains the Release Notes and Known Issues for System Generator for DSP 10.1.02.


For System Generator for DSP Release Notes from other versions, see (Xilinx Answer 29595).

Release Notes and Known Issues in System Generator for DSP 10.1.02

System Generator for DSP 10.1.02 is a minor update. Please read the documentation, because it answers questions you might have about changes to the functionality or the look from previous versions of System Generator for DSP. The System Generator User Guide is accessible in PDF format at:

Software Support

- What software is required to install System Generator for DSP? See (Xilinx Answer 17966).

System Generator Enhancements
Hybrid DCM-CE Support
In the 10.1 release, System Generator introduced a new clocking option to automatically include a Digital Clock Manager (DCM) in a design. This option was limited to designs with no more than three clock rates.

In this release, the clocking option has been enhanced to support designs with more than three clock rates. The additional rates are automatically supported with the Clock Enable (CE) methodology. For example, if a design has 6 clock rates, the highest three clock rates are supported with a DCM, and the lowest three clock rates are supported with the CE methodology.

MATLAB 2008a
MATLAB 2008a is now supported by System Generator. To install System Generator into MATLAB 2008a, after installing the service pack, launch the MATLAB chooser from the Start menu under Xilinx > DSP Tools and add MATLAB 2008a.

Xilinx DSP Blockset Enhancements
FIR Compiler 4.0
New block now available in System Generator with the following features:
- Extended data and coefficient width range up to 49 bits.
- Polyphase filter bank support for channelizer applications and transpose multiply accumulate architecture.
- Capability to share control and coefficient memory resources for up to 16 parallel data paths.
- Virtex-5 and Spartan-3A DSP support added for distributed arithmetic architecture.
- This block supports all the features supported by FIR Compiler LogiCORE v4.0.

Divider Generator 2.0
- New block now available in System Generator that generates arithmetic division algorithms for integer division.
- Optional operand widths up to 54-bit wide, synchronous controls, and selectable latency.
- Supports Virtex-4, Virtex-5, and Spartan-3A DSP for both radix-2 integer division and high-radix division algorithms.

Xilinx Block Set Issues

- Why does the DSP48 Opmode block have invalid characters reading "PCIN>>17" instead of "PCIN>>17"? See (Xilinx Answer 30790).
- Why does the post-MAP resource estimation return zero for all resources except IOBs? See (Xilinx Answer 30675).

General Issues

- Why does Simulink report that my output type is obsolete in MATLAB 2008a when I have a signal width greater than 54 bits? See (Xilinx Answer 31255).
- When using System Generator on a 64-bit XP machine, why do I receive a message stating, "There is a problem with your Xilinx ISE installation or with your Xilinx environment variable" and "could not run java.exe"? See (Xilinx Answer 29512).
- When trying to use System Generator on Windows Vista, why do I receive an error stating "gcc.exe: installation problem, cannot exec 'cc1': No such file or directory. Error occurred during Simulation Initialization"? See (Xilinx Answer 30977).
- I cannot add my System Generator Project (.SGP) file to my ISE Project Navigator project. Why? See (Xilinx Answer 30676).
- Simulation does not use the automatically generated Verilog testbench and stimulus files. See (Xilinx Answer 30308).
- Why do I see an instantiated register called "xlpersistentdff" in a System Generator for DSP design? See (Xilinx Answer 24257).
- JTAG Hardware Co-Sim with non-Xilinx parts in the chain causes error. See (Xilinx Answer 19599).
- Why do I receive "Error 0001: caught standard exception" error when using IBM Clear Case? See (Xilinx Answer 24263).
- Why do post-PAR simulation mismatches occur when running a design at faster than 200 MHz? See (Xilinx Answer 24268).
- I cannot generate an NGC, Bitstream, Timing Analysis, or Hardware in the Loop target when using Synplify as my synthesis tool. Why? See (Xilinx Answer 24273).
- Why are there simulation mismatches at the beginning of the HDL simulation generated from System Generator for DSP when Synplify is used for synthesis? See (Xilinx Answer 29170).
- Why does the design fail to generate when using a FIFO block, From FIFO block, or To FIFO block in the design, and the target path is more than 160 characters? See (Xilinx Answer 23614).
- Why do I receive the message "xledkpostgen>PLBPcoreBuilder at 234" when netlisting my EDK PCORE design from System Generator? See (Xilinx Answer 31068).
- Why do I receive "Error in 'Design/block' while executing C MEX S-function 'sysgen', (mdlTerminate), at time 10. MATLAB error message: Unexpected unknown exception from MEX file" when I simulate my System Generator model? See (Xilinx Answer 31095).
- Why do I receive the message "Failed to execute command "project set {Synthesis Tool} {Synplify Pro (VHDL/Verilog)}"" when trying to use Synplify Pro for my synthesis tool form System Generator? See (Xilinx Answer 31112).
- During simulation of my FFT v5.0 design why do I receive the error "FFT simulation did not complete successfully" when my FFT is configured for dynamic transform size? See (Xilinx Answer 31271).
- Why is my reset signal on my FIFO not behaving the same in hardware as it did in software? See (Xilinx Answer 31294).
- For a multi-channel implementation, why is the FIR Compiler Chan_In output offset by a clock cycle from the actual channel it is accepting? See (Xilinx Answer 31454).
- When I use the CIC Compiler filter with an input data rate less than the system clock rate controlled by ND, I see mismatches between the simulation results in System Generator versus hardware co-simulation. See (Xilinx Answer 31455).
- Why am I unable to see the expected behavior after recompiling my C-code for my EDK Processor block when my EDK project uses SDK for compilation? See (Xilinx Answer 31622).

AR# 31216
Date 09/17/2008
Status Active
Type General Article
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