Keyword: TEMAC, tri-mode EMAC, Virtex-4, Virtex-5, RGMII
I am using a xps_ll_temac in RGMII v1.3 mode. I found the transmit data is driven out on the rising edge, but from Figure 56 (in DS537, v1.5), it looks like on the ODDR of RGMII_TXC D1 is set to 0 and D2 to 1 which would produce an inverted clock, so data should be driven on the falling edge of the clock based on the data sheet. Which one is correct?
The core design is correct and the data sheet is incorrect.
The data sheet will be corrected in EDK 10.1 SP3.