When I use the ML455, the MPMC does not work, or the following error occurs:
ERROR:Place:604 - The I/O components "mpmc_0_DDR_Clk_pin<1>" and "mpmc_0_DDR_Clk_n_pin<1>" are the P- and N-sides of a
differental I/O pair. The component "mpmc_0_DDR_Clk_pin<1>" needs to be placed in a IOBM site and component
"mpmc_0_DDR_Clk_n_pin<1>" in the adjacent IOBS site within the same I/O tile. The following issue has been detected:
All of the logic associated with this structure is locked and the relative placement of the logic violates the
structure. The problem was found between the relative placement of IOB mpmc_0_DDR_Clk_n_pin<1> at site IOB_X2Y15 and
IOB mpmc_0_DDR_Clk_pin<1> at site IOB_X2Y14.
It is possible to allow location constraints to override this rule by setting the environment variable
How do I resolve this issue?
This problem is caused by a pin-out issue on the ML455. The DDR CLK1 p and n sides residing at AF7 and AF8, respectively, drive the inverted polarity of the SODIMM CLK1 and CLK1#. Using the correct pin-out causes the above error. Swapping the pin locations will resolve the error, but this causes an inverted clock to be driven to the memory, which results in the memory not finishing calibration.
This issue can be resolved by inverting the polarity of CLK1 inside of the FPGA.