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AR# 31286

10.1 EDK, MPMC v4.02.a - "ERROR:ConstraintSystem:58 - Constraint does not match any design objects"

Description

After I convert a Virtex-5 DDR (not DDR2) MIG UCF to a MPMC MIG PHY UCF, the following error occurs during NGDBuild:

"ERROR:ConstraintSystem:58 - Constraint <NET

"u_ddr1_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs*.gen_phy_dqs_iob_gate.u_i

ob_dqs/dqs_comb" MAXDELAY = 590 ps;>

[system.ucf(93)]: NET

"u_ddr1_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs*.gen_phy_dqs_iob_gate.u_i

ob_dqs/dqs_comb" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <NET

"u_ddr1_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs*.gen_phy_dqs_iob_gate.u_i

ob_dqs/gate_dqs" MAXDELAY = 1060 ps;>

[system.ucf(95)]: NET

"u_ddr1_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs*.gen_phy_dqs_iob_gate.u_i

ob_dqs/gate_dqs" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <NET

"u_ddr1_top/u_mem_if_top/u_phy_top/u_phy_io/gen_phy_calib_gate.u_phy_calib/en

_dqs*" MAXDELAY = 1.0 ns;>

[system.ucf(99)]: NET

"u_ddr1_top/u_mem_if_top/u_phy_top/u_phy_io/gen_phy_calib_gate.u_phy_calib/en

_dqs*" does not match any design objects."

How do I resolve this issue?

Solution

Updated convert scripts are available from (Xilinx Answer 29261). Rerun the conversion scripts and update the EDK UCF with the results.

This issue is scheduled to be fixed starting with the scripts from MPMC v4.03.a, to be released in EDK 10.1 Service Pack 3.

AR# 31286
Date Created 07/09/2008
Last Updated 12/15/2012
Status Active
Type General Article