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AR# 31294

11.1 System Generator for DSP - Why is the reset signal on my FIFO not behaving the same in hardware as in software?


In System Generator simulation, the reset behaves as a level-sensitive signal. However, in HDL simulation (and in hardware), it is edge-sensitive.


This is due to a change of behavior in the FIFO Generator IP Core which is used for the FIFO Block in System Generator for DSP. The new behavior is that the reset signal is edge-sensitive, which has not been reflected in System Generator.  


This will be addressed in a future release of System Generator.

AR# 31294
Date 05/22/2014
Status Archive
Type General Article
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