In System Generator simulation, the reset behaves as a level-sensitive signal. However, in HDL simulation (and in hardware), it is edge-sensitive.
This is due to a change of behavior in the FIFO Generator IP Core which is used for the FIFO Block in System Generator for DSP. The new behavior is that the reset signal is edge-sensitive, which has not been reflected in System Generator.
This will be addressed in a future release of System Generator.