I have a project with a schematic (.sch) file selected as the top-level module.
When synthesizing the design, one of the sub_modules in the design gets synthesized as top_level instead of the top_level module.
The sub_module selected seems to be randomly selected, but is usually a VHDL, Verilog, or source type other than schematic.
The Hierarchy shown in the Project Navigator Sources window is shown correctly.
New projects do not exhibit this behavior, but a project might become corrupted after running the Clean-up Project Files process.
An additional symptom of this project corruption is that changes to schematic source files do not put dependent processes such as Synthesis and Implementation "out of date".
This issue occurs because the internal view of the ISE project is being misread and becomes partially corrupted.
This causes the parser to select the wrong top-level module to send to synthesis.
In most cases, the project can be restored to its correct state by generating a project Tcl script (Project -Generate Tcl Script ...), and then sourcing the Tcl script to regenerate the project. However, this is typically a temporary fix.
A patch for this issue is available at:
The patch is applicable to ISE 10.1 with Service Pack 3 (ISE 10.1.03) on Windows 32-bit, Windows 64-bit, Linux 32-bit, and Linux 64-bit platforms.
The pn_sch_10_3fix.zip file contains six files:
Please extract to the root of your ISE 10.1 installation directory (for example, C:\Xilinx\10.1\ISE).
You can extract all files or only the .txt, .tcl and the linked library (.so or .dll) for the platform being used.
Original files in the respective directories should be moved or renamed before copying the archived files to these locations.
This fix addresses two ISE project corruption issues which occur with ISE 10.1.03 schematic-based projects after running Clean-up Project Files: