We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 31387

LogiCORE CAM v6.1 - An error occurs when I attempt to load the VHDL Behavioral model in ModelSim 6.3c


When using ModelSim 6.3c with the CAM v6.1 Core, I receive an error similar to the error message below when the VHDL behavioral model is loaded:



(vopt-1272) Length of expected is 7; length of actual is 128.


The error above occurs during the optimization stage when the optimization option in vsim, '-vopt' is turned on by default.

To avoid the above failure, use the '-novopt' option in the vsim command line when using ModelSim 6.3c, or use ModelSim 6.3e or later.

AR# 31387
Date 12/15/2012
Status Active
Type General Article
Page Bookmarked