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AR# 31437

10.1.02 System Generator for DSP - Why do I receive the error message "standard exception: XNetlistEngine: An exception was raised" when generating a design with the FIR Compiler?


Keywords: SysGen, FIR, non-symmetric, multiple columns, DSP48, systolic

When my System Generator design contains a FIR Compiler, it errors out during generation with the following message:

"standard exception: XNetlistEngine:
An exception was raised:
com.xilinx.sysgen.netlist.NetlistInternal: couldn't run "C:/Xilinx/10.1/ISE/bin/nt/coregen.exe -p . -b coregen.cgxco 1>C:/xprojects/cases/sean/large_fir/FIR_design_test/netlist/sysgen/coregen_ZID3/coregen_tmp/second_pass_coregen.txt 2>&1" at C:\xprojects\cases\sean\large_fir\FIR_design_test\netlist\sysgen\masterScript57730.pl line 700"


This error in System Generator can occur when CORE Generator fails to generate the FIR Compiler. The best way to identify the cause is to open up the coregen.log file, which should be located in the output netlist directory in the sub-folder:

This log file will provide further information as to why the generation failed, for instance:

ERROR:coreutil - Exception caught when running XST synthesis!
ERROR:coreutil - Failure to generate output products
ERROR:coreutil:424 - An error occurred while running Java. Please examine the
console or coregen log file for a specific IP related error.
For more information please search the Xilinx Answers Database for this
error: http://www.xilinx.com/supportFinished Regenerating.
ERROR:sim:57 - Error found during generation

In this case core generation failed because of a memory problem. Generating the core on a machine with more memory might resolve this problem.
AR# 31437
Date 08/11/2008
Status Active
Type General Article
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