AR# 3145

Foundation XVHDL, NGDBuild: Warning:basnu-The input pad net "<nonclk signal>" is driving one or more clock loads, but is not using a dedicated clock buffer

Description

Keywords: ngdbuild, xvhdl, clock, bufg, bufgp, bufgs

Urgency: Standard

General Description:

NGDBUILD may give the following warnings/error:

"WARNING:basnu - Multiple blocks named "view_1/<nonclk_port>"
in block "<vhdl file>".

WARNING:basnu - The input pad net "<nonclk_port>" is driving
one or more clock loads, but is not using a dedicated clock
buffer.


ERROR: basnu - logical net "<nonclk_port>" has both active and
tristate drivers"
or,
"ERROR: basnu - logical net "<nonclk_port>" has multiple
drivers"

when instantiating IBUFs and BUFGs with VHDL in Foundation.

Solution

One cause of this problem is not using upper-case to declare the
component and the ports on the instantiated components.

IE:

component BUFGS
port(I:in bit;
O:out bit);
end component;
AR# 3145
Date 01/02/2000
Status Archive
Type General Article