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Foundation XVHDL, NGDBuild: Warning:basnu-The input pad net "<nonclk signal>" is driving one or more clock loads, but is not using a dedicated clock buffer
Keywords: ngdbuild, xvhdl, clock, bufg, bufgp, bufgs
NGDBUILD may give the following warnings/error:
"WARNING:basnu - Multiple blocks named "view_1/<nonclk_port>"
in block "<vhdl file>".
WARNING:basnu - The input pad net "<nonclk_port>" is driving
one or more clock loads, but is not using a dedicated clock
ERROR: basnu - logical net "<nonclk_port>" has both active and
"ERROR: basnu - logical net "<nonclk_port>" has multiple
when instantiating IBUFs and BUFGs with VHDL in Foundation.
One cause of this problem is not using upper-case to declare the
component and the ports on the instantiated components.
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