AR# 31462: 10.1 Spartan-3A PAR - ERROR:Place:1012 - A clock IOB / DCM component pair have been found that are not placed at an optimal clock IOB / DCM site pair
10.1 Spartan-3A PAR - ERROR:Place:1012 - A clock IOB / DCM component pair have been found that are not placed at an optimal clock IOB / DCM site pair
Keywords: DCM, placement, placed, optimal
My design is failing during placement with the following error. The error message indicates that the DCM is being placed on the opposite side of the device from the locked IOB. The DCM is not constrained and a suitable DCM site was available. Why did the placer choose this placement and then error out?
ERROR:Place:1012 - A clock IOB / DCM component pair have been found that are not placed at an optimal clock IOB / DCM site pair. The clock component <infrastructure_top0/clk_dcm0/DCM_INST1/DCM_SP> is placed at site <DCM_X0Y0>. The clock IO/DCM site can be paired if they are placed/locked in the same quadrant. The IO component <sys_clk> is placed at site <P130>. This will not allow the use of the fast path between the IO and the Clock buffer. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a WARNING and allow your design to continue. However, the use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. A list of all the COMP.PINs used in this clock placement rule is listed below. These examples can be used directly in the .ucf file to override this clock rule. < NET "sys_clk" CLOCK_DEDICATED_ROUTE = FALSE; > < PIN "infrastructure_top0/clk_dcm0/DCM_INST1/DCM_SP.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE; >
This problem occurred because the clock placer failed to correctly identify the side of the chip where each DCM site was located. The problem can be avoided by manually constraining the DCM to a valid site.
This problem can occur for all Spartan-3 families.