We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 31504

10.1 Virtex-4 PLACE - Design fails to either fit or route due to poor clock region allocation


My design fails to fit even though the overall utilization is low and I have not constrained the slice logic. What could be causing this failure?

"ERROR:Place:543 - This design does not fit into the number of slices available in this device."

Unplaced instances by type:

FF 5694 (5.1%)

The following instances are the last set of instances that failed to place:

0. FF I_fpga_6_6/zwire_231770

1. FF I_fpga_6_6/zwire_231750

2. FF I_fpga_6_6/zwire_231753


Although the designer may not have consciously constrained the slice logic, any Virtex-4 design with more than eight global clocks will be automatically area constrained by the "clock placer" algorithm to ensure that no more than eight clock domains have loads in each clock region. A problem has been identified where the clock placer does a poor job of clock region allocation. The result can be that the largest clock domains are not given sufficient clock regions to place into. This can result in either a failure to fit the design (ERROR:Place:543 ) or in poor quality of results due to the limited options available to the placer.

A short term fix will be available in ISE version 10.1 sp3, currently scheduled for late September. A more complete fix is scheduled for ISE version 11.1. Meanwhile, a work-around is to manually constrain the smaller clock domains in the design to a small number of clock regions. This will cause the clock placer to allocate a larger amount of clock regions to the larger clock domains.

AR# 31504
Date 12/15/2012
Status Active
Type General Article
Page Bookmarked