This Answer Record contains the Release Notes for the LogiCORE Embedded Tri-mode Ethernet MAC Wrapper v1.5, which was released in ISE 10.1 IP Update 3 and includes the following:
- New Features
- Bug Fixes
- Known Issues
For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at: http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf
- Supports automatic generation of HDL wrapper files for the Virtex-5 LXT Tri-Mode Ethernet MAC
- Instantiates user-configurable Ethernet MAC physical interfaces (GMII, MII, RGMII, SGMII and 1000Base-X PCS/PMA configurations are supported)
- Provides a FIFO-based example design
- Provides a demonstration testbench for the selected configuration
- Support added for Virtex-5 TXT devices
- Attributes update for Virtex-5 GTX
-The VLAN, LTCHECK, HALF-DUPLEX, and INBANDFCS GUI selections were not always set correctly in HDL wrappers. For more information, see (Xilinx Answer 30816). This issue has been resolved.
- Virtex-5 LXT/SXT ES silicon requires transmit signals between the fabric and GTP to be registered and locked down to meet timing. These registers are not included in version v1.4 of the core. If LXT/SXT ES silicon is being used, the RocketIO wrapper files can be regenerated with the GTP wizard.
- Virtex-5 Functional or Timing Simulation. In (UniSim) functional simulation or (SimPrim) timing simulation, if TXPOWERDOWN#_IN is "X," this causes GTP outputs TXN/TXP to always be "X." If TXPOWERDOWN#_IN never goes to "X," the problem does not occur. For more information, see (Xilinx Answer 24677).
- In 10.1 SimPrim, Post-PAR timing simulation, the simulation does not always work as expected. For more information, see (Xilinx Answer 30815).
- There have been some attributes updates to the GTX wrappers since the core was released. For more information, see (Xilinx Answer 30577).
- In 1000BASE-X or SGMII mode, the GUI allows you to select the default for the PHY reset and power-down attributes. This GUI selection does not actually have any effect on the generated wrappers. In 1000BASE-X or SGMII mode, the wrappers always set the PHY reset and power-down attributes to FALSE.
- (Xilinx Answer 32186) 16-bit 1000BASE-X Verilog RX FIFO could incorrectly overflow.
- (Xilinx Answer 31860) Virtex-4/Virtex-5 Embedded Tri-Mode Ethernet MAC - Problems switching from 10/100 Mbps to 1G GMII operation