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AR# 31521

Virtex-4/-II Pro Aurora v3.0 - Release Notes and Known Issues for ISE 10.1 IP Update 3 (IP_10.1.3)

Description

This answer record contains the release notes for the Virtex-4/Virtex-II Pro Aurora v3.0 Core released with ISE 10.1 IP Update 3.

Solution

NEW FEATURE

- With Simplex timer option in GUI.

RESOLVED ISSUES

- Aurora XMDF file contains paths to files that were not generated.

- Non-standard parameterization in *_veo.ejava and *_vho.ejava.

- Aurora v2.9: move attributes to top level for more flexibility.

- Add X_CORE_INFO to Aurora8B10B supporting Virtex-II Pro and Virtex-4 FX.

- Soft_error from error detection circuit connected to PCS_RESET of GT11_init state mach.

- Rounding errors in REFCLK values.

- User Guide UG061 generated by CORE Generator is corrupted.

- UNISIM library library declaration missing in the aurora_phase_align.vhd.

- Usage of component_name to control configurations is non-standard.

- Virtex-4 USRCLKs have the same definition as that of Virtex-II Pro in UG061.

- Comments mention incorrect value set for TXPOST_TAP_PD for Loopback configuration.

- Certain reference clock speeds result in rounding errors when simulating example.

- Error in UCF file LOC constraints.

- Incorrect ISE flow provided in Aurora getting started UG173.

- VHO file is empty.

- Virtex-4 Aurora - Does not work at high speeds.

- Virtex-4 Aurora - An "all_soft_error_i" causes the core to reset itself.

- Aurora Wizard v2.7 outputting incorrect UCF for Virtex-4 FX60.

- Top level graphic has TXP/TXN and RXP/RXN reversed.

- Instantiation template is generated, but is left without a port listing.

- Aurora does not hold GSR long enough in post-PAR simulations.

- RXLOCK and TXLOCK are optimized out of example design.

- LOOPBACK port is hard coded for a simplex design.

- Aurora Wizard: MGT selection GUI not intuitive and needs more explanation.

- IP symbol pin ranges set to expressions and not values.

KNOWN ISSUES

- Hardware validation constrained by number of lanes available in ML423 boards. Lanes higher than 16 are not fully tested.

- Designs with REF_CLK input as 262.5MHz frequency have issues in Link Up. DCM have issues for this frequency. Refer to (Xilinx Answer 23624) for a work-around method.

AR# 31521
Date Created 09/22/2008
Last Updated 12/15/2012
Status Active
Type General Article