When I drag and drop a level of hierarchy from Floorplan Editor into the design, a single location is added for FIFOs and block RAMs.
Here is an example of a constraint that Floorplan Editor creates:
AREA_GROUP "AG_example" RANGE = SLICE_X17Y245:SLICE_X12Y240,FIFO16_X1Y30;
The tools are expecting a range and are receiving a single location.
To work around this issue, manually edit the UCF to read:
AREA_GROUP "AG_example" RANGE = SLICE_X17Y245:SLICE_X12Y240,FIFO16_X1Y30:FIFO16_X1Y30;
This issue is scheduled to be fixed in Service Pack 3 for ISE 10.1.