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AR# 31557

LogiCORE FIFO Generator v4.4 - Release Notes and Known Issues for ISE 10.1 IP Update 3 (IP_10.1.3)

Description

Keywords: CORE Generator, IP, update, 10.1i, IP0_K, FIFO, fifogen, asynchronous, synchronous, common, clocks, memory, block RAM, BRAM, RAMB16, FIFO16, asynch, asymmetric, non-symmetric, first, word, fall, through, fwft

This Release Notes and Known Issues Answer Record is for the FIFO Generator v4.4, released in ISE 10.1 IP Update 3, and contains the following information:

- General Information
- New Features
- Bug Fixes
- Known Issues
- Device Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at:
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

Solution

General Information

(Xilinx Answer 22014) When using FIFO Generator Core, the allowed data count width is less than it should be
(Xilinx Answer 22722) FIFO Generator Core now includes a User Guide in addition to a data sheet. Where can I find the User Guide for the FIFO Generator?
(Xilinx Answer 24712) How do I test user logic that triggers ECC SBITERR and DBITERR outputs in FIFO Generator?
(Xilinx Answer 30029) Setup/Hold time violations occur in the Unconstrained Path Report
(Xilinx Answer 31144) Differences between FIFO v4.x cores and v3.x (and prior) cores

New Features in v4.4

- Option to enable/disable timing violations on cross clock domain registers
- Enhanced data width support - up to 1024
- Virtex-5 TXT device support
- Summary of simulation model chosen and its limitations in FIFO generator CORE Generator GUI summary page

Bug Fixes in v4.4

(Xilinx Answer 30221) Customization GUI incorrectly advertises FWFT support for certain configurations - CR 458157
(Xilinx Answer 30571) Synchronous reset (SRST) does not affect DOUT or EMPTY - CR 467318
- In the FIFO Generator User Guide, the behavior of the asynchronous reset is not clearly defined - CR 473545
- In the FIFO Generator User Guide, reset description in Table 2-4 does not clarify its behavior - CR 472155
- In the FIFO Generator User Guide, simultaneous assertion of FULL/EMPTY flag behavior for non built-in independent clock FIFO is not defined - CR 467555
- In the FIFO Generator User Guide, the behavior of the write operation for a FIFO with independent clock (Figure 4-6) is incorrect - CR 467514
- In the FIFO Generator GUI, depth selection for Virtex-5 built-in FIFO is incorrectly defined - CR 440839

Known Issues in v4.4

(Xilinx Answer 32032) Why is FWFT not available for Distributed RAM configurations?
(Xilinx Answer 24003) NC-Sim warning occurs when targeting Virtex-5
(Xilinx Answer 23691) Behavioral simulation models are not supported for built-in FIFO configuration
(Xilinx Answer 20291) During simulation X_FF RECOVERY and SETUP warnings occur
(Xilinx Answer 20271) Simulation error occurs on RESET
(Xilinx Answer 30226) When writing to an EMPTY FIFO, PROG_FULL might assert earlier than expected
(Xilinx Answer 31379) When importing an XCO file, user cannot change read/write clock frequencies with Built-in FIFO
(Xilinx Answer 31380) The first word does not fall through in structural simulation of a Common Clock BRAM with FWFT
(Xilinx Answer 31381) Empty flag does not assert in Common Clock (block RAM based) behavioral model simulation


FIFO Generator v4.3 Known Issues

-The FIFO Generator v4.3 is now obsolete. Please upgrade to the latest version of the core. For information on existing FIFO Generator v4.3 issues, see (Xilinx Answer 30056).

FIFO Generator v4.2 Known Issues

-The FIFO Generator v4.2 is now obsolete. Please upgrade to the latest version of the core. For information on existing FIFO Generator v4.2 issues, see (Xilinx Answer 29246).

FIFO Generator v4.1 Known Issues

-The FIFO Generator v4.1 is now obsolete. Please upgrade to the latest version of the core. For information on existing FIFO Generator v4.1 issues, see (Xilinx Answer 25458).

FIFO Generator v3.3 Known Issues

-The FIFO Generator v3.3 is now obsolete. Please upgrade to the latest version of the core. For information on existing FIFO Generator v3.3 issues, see (Xilinx Answer 24552).

FIFO Generator v3.2 Known Issues

-The FIFO Generator v3.2 is now obsolete. Please upgrade to the latest version of the core. For information on existing FIFO Generator v3.2 issues, see (Xilinx Answer 23847).

FIFO Generator v3.1 Known Issues

-The FIFO Generator v3.1 is now obsolete. Please upgrade to the latest version of the core. For information on existing FIFO Generator v3.1 issues, see (Xilinx Answer 23490).

FIFO Generator v2.3 Known Issues

-The FIFO Generator v2.3 is now obsolete. Please upgrade to the latest version of the core. For information on existing FIFO Generator v3.1 issues, see (Xilinx Answer 22302).


Revision History

09/19/2008 - Initial Release
01/09/2009 - Added AR 32032 to Known Issues
AR# 31557
Date Created 09/04/2008
Last Updated 01/08/2009
Status Active
Type General Article