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AR# 31558

LogiCORE IP CAM (Content Addressable Memory) v6.1 - Release Notes and Known Issues for ISE 10.1 IP Update 3 (IP_10.1.3)

Description

This Release Note and Known Issues Answer Record is for the CAM v6.1 released in ISE 10.1 IP Update 3 and contains the following information:

  • General Information
  • New Features
  • Bug Fixes
  • Known Issues
  • Device Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide (XTP025) at:
http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf

Solution

NOTE:The CAM v6.1 Core has been discontinued in ISE DesignSuite 12.1.To use the core in ISE 12.1, see (Xilinx Answer 35370).

New Features in v6.1

  • Virtex-5, Spartan-3E/-3A/-3A DSP FPGA support
  • XST inference-based implementation

Bug Fixes in v6.1

  • The depicted timing of the EN assertion for an SRL16 write operation in Figure 5 of the data sheet is incorrect (CR 303692)

Known Issues in v6.1

CAM v5.1 Known Issues

  • CAM v5.1 is now obsolete. Please upgrade to the latest version of the core. For information on existing CAM v5.1 issues, see (Xilinx Answer 20218).
AR# 31558
Date Created 09/04/2008
Last Updated 05/19/2012
Status Active
Type Release Notes