This Release Note and Known Issues Answer Record is for the LogiCORE Initiator/Target for PCI-X v6.8 released in ISE 10.1 IP Update 3 and contains the following information:
- General Information
- New Features
- Bug Fixes
- Known Issues
For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at: http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf
The LogiCORE PCI v6.8 supports Virtex-5 and newer architectures only. For all other devices, use the v5.166 PCI-X Core. For more information on this core, refer to (Xilinx Answer 31569).
- Added support for 10.1sp3
- CR472742, 478110: Incorrect DESKEW_ADJUST values in some UCFs caused timing issues.
- See (Xilinx Answer 30518) regarding use of RCLK in embedded designs for PCI-X 133 MHz.
-With newer versions of ModelSim, when running the example simulation it might be necessary to add this option to the vsim command:
vsim -voptargs="+acc" -L unisims_ver -t ps work.TEST_TB glbl
This argument instructs ModelSim not to optimize internal signals in the simulation model.
06/17/2009 - Added MTI note on vsim command.
09/19/2008 - Initial release.