During the generation of the programing file (JEDEC file), the following message is displayed.
WARNING: Cpld: 816 - At least one signal 'Q ' from the tmv file is missing in the database. Please check the report file to verify that this signal exists. Also, please verify that its case matches.
This warning will occur if a name in the .tmv file does not match any name in the design netlist. A common cause of this warning is when the bus delimiter in the design netlist are inconsistent with the delimiters in the .TMV file. When compiling an ABEL file with test vectors, the .tmv file is written out with square brackets '' for bus delimiters. However, the default bus delimiters used in XST synthesis are angle brackets '<>'. Because of this, the signals do not match, resulting in the warning message. "Don't care" is inserted into the JEDEC file test vector for all these signals.
If you are using Verilog or VHDL as the project source, you can define Bus Delimiter globally in Project Navigator -> Process Properties -> Synthesis Options -> Bus Delimiter.
If you are using the ABEL (XST) flow, the option to set the Bus Delimiter is not provided from the Project Navigator Compile options.
To work around this, do one of the following:
- Manually change the bus delimiter in the .TMV file to "<>" after the ABEL file and test vectors have been compiled.
- Define Bus Delimiter globally using the -bus_delimiter option in the .xst file and then write protected this file, so that ISE could not undo the changes. Then, run the remaining design flow from command line.