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AR# 31579

MIG v2.3, v3.0 - Virtex-5 QDRII "ERROR:Place:899 - The following IOBs use DCI and have been locked to the I/O bank #"

Description

In a Virtex-5 QDRII multi-controller design, where one controller is using DCI Cascade and the second controller is not using DCI Cascade, the design fails during MAP with error messages similar to the following: 

ERROR:Place:899 - The following IOBs use the Digitally Controlled Impedance feature (DCI) and have been locked (LOC constraint) to the I/O bank 21. This feature requires the VRN and VRP pins within the same I/O bank to be connected to reference resistors. 

The following VR pins are currently locked and can't be used to supply the necessary reference. 

IO Standard: Name = HSTL_I_DCI_18, VREF = 0.90, VCCO = 1.80, TERM = SPLIT 

List of locked IOB's: 

c3_qdr_cq_n(0) 

c3_qdr_q(10) 

c3_qdr_q(11) 

c3_qdr_q(12) 

c3_qdr_q(13) 

c3_qdr_q(14) 

c3_qdr_q(15) 

c3_qdr_q(16) 

c3_qdr_q(17) 

c3_qdr_cq(0) 

c3_qdr_q(0) 

c3_qdr_q(1) 

c3_qdr_q(2) 

c3_qdr_q(3) 

c3_qdr_q(4) 

c3_qdr_q(5) 

c3_qdr_q(6) 

c3_qdr_q(7) 

c3_qdr_q(8) 

c3_qdr_q(9) 

 

List of occupied VR Sites: 

VR site IOB_X0Y135 is occupied by comp c4_qdr_sa(17) 

VR site IOB_X0Y134 is occupied by comp c4_qdr_sa(16) 

 

In a Virtex-5 QDRII multi-controller design, where one controller is using DCI Cascade and the second controller is not using DCI Cascade, MIG should always reserve VRN/VRP pins for the second controller data read banks in order to apply the DCI Standards. 

For the second controller's data read bank selection, MIG should only allow selection of banks where VRN/VRP pins are vacant. 

Currently, MIG allows allocation for data read banks regardless of whether the bank has vacant VRN/VRP pins.  

In the above error message, c3 and c4 pre-pended to the signal names indicate the controller numbers.

C3 has the DCI Cascade option disabled; therefore, the VRN/VRP pins are not utilized. 

The address pins for c4 are allocated to the vacant VRN/VRP pins which is not allowed. 



Solution

This issue is fixed in MIG v3.1.


To work around this issue, the output MIG UCF file will have the DCI Cascade syntax ('CONFIG_DCI_CASCADE = master and slave banks information") for the controllers with DCI Cascade enabled. 

For the design to pass MAP, the data read banks of the second controller which do not have DCI Cascade enabled must be included in the constraint as the slave banks. 

For the error message provided above, this is the DCI Cascade syntax in the MIG generated UCF file: 

CONFIG DCI_CASCADE = "27 29 33"; 

In the above syntax, '27' is the master bank. '29' and '33' are the c4 controller data read banks (slave banks). 

Bank '21' is the c3 controller data read bank. 

For the design to pass, bank '21' must be included as a slave bank. To do this, modify the DCI Cascade syntax as shown below: 

CONFIG DCI_CASCADE = "27 29 33 21"; 

You will need to ensure that the master bank and all of the slave banks belong to one single column of banks.

AR# 31579
Date Created 09/08/2008
Last Updated 07/30/2014
Status Active
Type General Article
Devices
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