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AR# 31580

MIG v2.3 - Virtex-5 QDRII, DDRII, Multi-Controller: Provided active high reset logic does not work properly in simulation

Description

When using the Virtex-5 QDRII SRAM, DDRII SRAM and Multi-Controller designs, the provided active high reset logic does not work correctly if the MIG "Use DCM" option was not selected (without DCM design).

Solution


This is an issue with the simulation testbench provided by MIG.

The DCM instantiated in the simulation testbench does not come out of reset during simulation.

This issue is resolved in MIG v3.0.


This problem occurs because the DCM primitive instantiated in the simulation testbench (sim_tb_top.v/.vhd) port maps the incorrect reset signal. 

To work around this issue, you must modify the port mapping to the correct reset signal.

Below are the Modifications which need to be made in sim_tb_top.v/.vhd:


DDRII SRAM - Verilog  

Current implementation:  

.RST ( user_reset_in )

Fix:  

.RST ( ~sys_rst_n )



DDRII SRAM - VHDL  

Current implementation: 

RST => user_reset_in

Fix:  

signal not_sys_rst_n; 

begin 

not_sys_rst_n <= not (sys_rst_n); 

U_DCM_ADV : DCM_ADV 

port map(  

RST => not_sys_rst_n 

);



QDRII SRAM - Verilog 

Current implementation:  

.RST ( user_reset_in )

Fix: 

.RST ( ~sys_rst )



QDRII SRAM - VHDL 

Current implementation:  

RST => user_reset_in

Fix:  

signal not_sys_rst; 

begin 

 

not_sys_rst <= not (sys_rst); 

 

U_DCM_ADV : DCM_ADV 

port map(  

RST => not_sys_rst 

);



Multi-Controller - Verilog 

Current implementation:  

.RST ( sys_rst_in )

Fix:  

.RST ( ~sys_rst_n )  

 



Multi-Controller - VHDL 

Current implementation:  

RST => sys_rst_in 

 

Fix:  

signal not_sys_rst_in; 

begin 

 

not_sys_rst_in <= not (sys_rst_in); 

port map(  

RST => not_sys_rst_in 

);

AR# 31580
Date Created 09/08/2008
Last Updated 07/30/2014
Status Active
Type General Article
Devices
  • Virtex-5 FXT
  • Virtex-5 LX
  • Virtex-5 LXT
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  • Virtex-5 SXT
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IP
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