AR# 31588

MIG v2.3, Virtex-5 DDR SDRAM - Simulation remains in reset if the value of the parameter RST_ACT_LOW is changed from '1' to '0' in the simulation test bench (sim_tb_top.v/.vhd)

Description

There is an issue simulating the MIG v2.3 Virtex-5 DDR SDRAM design. 

The simulation remains in reset if the value of the parameter RST_ACT_LOW is changed from '1' to '0' in the simulation test bench (sim_tb_top.v/.vhd). 

This issue will be resolved in MIG v3.0.

Solution

To work around this issue in Verilog, the RST_ACT_LOW parameter must be port mapped to the top-level rtl file (that is, DDR_SDRAM.v/.vhd for DDR SDRAM) in the SIM_TB_TOP module.

To work around this issue in VHDL, a CONSTANT declaration of RST_ACT_LOW should be made in the component declaration of the top-level rtl file (for example, DDR_SDRAM.v/.vhd for DDR SDRAM)

Similarly, the parameter should be port mapped in the instance port mapping in the SIM_TB_TOP module.

AR# 31588
Date 07/23/2014
Status Active
Type General Article
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IP