The MIG v2.3 generated "user_design" for Spartan-3 Generation DDR/DDR2 SDRAM uses an incorrect hierarchy path for the fifo_we_clk constraint in the provided UCF.
This issue is also apparent in MIG v3.6 when using the Verify/Update tool to generate a design.
This is only true for designs generated using Left/Right banks.
The hierarchy path must be manually modified.
The provided UCF produces the following error during Translate:
This issue is to be resolved in MIG v3.0 when generating a new design.
To work around this issue, open the user_design UCF file located in the "par" directory.
The constraint below includes the incorrect path:
Replace the above constraint with the following: