AR# 31591

MIG v2.3 - Spartan-3 Generation DDR/DDR2 SDRAM: Incorrect hierarchy for the fifo_we_clk constraint in the provided user_design UCF


The MIG v2.3 generated "user_design" for Spartan-3 Generation DDR/DDR2 SDRAM uses an incorrect hierarchy path for the fifo_we_clk constraint in the provided UCF. 

This issue is also apparent in MIG v3.6 when using the Verify/Update tool to generate a design. 

This is only true for designs generated using Left/Right banks.

The hierarchy path must be manually modified. 

The provided UCF produces the following error during Translate: 

ERROR:ConstraintSystem:58 - Constraint <NET "main_00/top0/data_path0/data_read_controller0/gen_wr_en*fi...> [mig_23.ucf(43)]: NET  "main_00/top0/data_path0/data_read_controller0/gen_wr_en*fifo*_wr_en_inst/clk" does not match any design objects. 

WARNING:ConstraintSystem:56 - Constraint <TIMESPEC "TS_WE_CLK" = FROM "dqs_clk" TO "fifo_we_clk" 5 ns DA...> [mig_23.ucf(44)]: Unable to find an active 'TimeGrp' or 'TNM' or 'TPSync' or 'TPThru' constraint named 'fifo_we_clk'."

This issue is to be resolved in MIG v3.0 when generating a new design.


To work around this issue, open the user_design UCF file located in the "par" directory. 

The constraint below includes the incorrect path: 

NET "main_00/top0/data_path0/data_read_controller0/gen_wr_en*fifo*_wr_en_inst/clk" 
TNM_NET = "fifo_we_clk";  


Replace the above constraint with the following: 

NET "top_00/data_path0/data_read_controller0/gen_wr_en*fifo*_wr_en_inst/clk" 
TNM_NET = "fifo_we_clk";

AR# 31591
Date 10/14/2014
Status Active
Type Error Message