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AR# 31620

10.1 Virtex-5 MAP - ERROR:PhysDesignRules:1242 - Invalid connection used for ILOGIC


I see the following error when data is driven from the IODELAY block to the register of an ILOGIC block:

"ERROR:PhysDesignRules:1242 - Invalid connection used for ILOGIC. The ILOGIC comp

<input_flop> D pin signal <signal_driving_flop> is not driven from an I/O."


This error can occur when an IDELAY component is instantiated in an input circuit and there is also a conflicting IOB=NONE constraint applied somewhere else in the circuit. This causes pack to incorrectly configure the ILOGIC component with the delayed signal driving the D input pin rather than the DDLY pin, resulting in an invalid and unroutable connection.

To work around this issue, remove either the IDELAY instance or the conflicting constraint. It would also work to override the NONE constraint with a compatible constraint.


NET "abc/data_in" IOBDELAY = IFD;
AR# 31620
Date 12/15/2012
Status Active
Type General Article
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