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AR# 31623

10.1 Virtex-5 PLACE - Long carry chains taller than device or area group range are not aligned


My design failed to route successfully. I received the following PAR message. When I examine the problem signals in FPGA Editor, I see that the signals are all carry signals belonging to the same carry chain. None of the carry chain slices were aligned by the Placer. The design worked okay in ISE 9.2i. Why did this happen in ISE 10.1?

"ERROR:Route:471 -

This design is unrouteable. Router will not continue. To evaluate the problem please use fpga_editor. The nets listed

below can not be routed:

Unrouteable Net:armsub_top/security/modulo_exponent/modulo_multiply/shared_compare_less_than_result_cry[13]/O

Unrouteable Net:armsub_top/security/modulo_exponent/modulo_multiply/shared_compare_less_than_result_cry[21]/O

Unrouteable Net:armsub_top/security/modulo_exponent/modulo_multiply/shared_compare_less_than_result_cry[45]/O

Unrouteable Net:armsub_top/security/modulo_exponent/modulo_multiply/shared_compare_less_than_result_cry[53]/O

Unrouteable Net:armsub_top/security/modulo_exponent/modulo_multiply/shared_compare_less_than_result_cry[61]/O

(Repeated for many other carry signals)"


This problem, which is a regression from ISE 9.2i, occurs when a carry chain is either taller than the device or taller than the area group range that it is assigned to. Rather than breaking the carry chain into pieces small enough to place within the vertical limitations, the placer fails to align the carry chain at all.

This problem has been fixed in the latest 10.1 Service Pack available at:


The first service pack containing the fix is 10.1 Service Pack 3.

NOTE: In addition to installing the service pack, it is also necessary to set the following environment variable to fix this carry chain placement issue:





For general information about setting ISE environment variables, see (Xilinx Answer 11630).

AR# 31623
Date 12/15/2012
Status Active
Type General Article