Since upgrading to ISE 10.1 Service Pack 3, my design now fails due to the following DRC messages. These unused signals were trimmed by earlier versions of ISE. What has changed?
ERROR:PhysDesignRules:1577 - Illegal routing. The DCM_ADV block <dcm_0/dcm_0/Using_DCM_ADV.DCM_ADV_INST> has CLK output
pin <CLKFX> with incomplete or incorrect connectivity. Routing from the <CLKFX> pin to a BUFG, BUFGCTRL or PLL_ADV
block type was not found. The DCM_ADV CLK output pins can only route to BUFG, BUFGCTRL or PLL_ADV block types.
ERROR:PhysDesignRules:1720 - Incomplete connectivity. The pin <G1> of comp block
<compare_error_i> is used and partially connected to network
<compare_error0_i>. All networks must have complete connectivity to the comp
hierarchy and the connectivity for this pin must be removed or completed.
This problem is a known regression in ISE 10.1 sp3 and is caused by a problem with trimming rules at "keep hierarchy" boundaries. The problem will be fixed in ISE 11.1. Meanwhile, the problem can be avoided by either disabling keep hierarchy during MAP (map -ignore_keep_hierarchy) or by setting the following environment variable:
setenv XIL_MAP_DISABLE_KH_NO_CLIP 1
For general information about setting ISE environment variables, see (Xilinx Answer 11630).