Known Issue: v1.9, v1.8, v1.7.1, v1.6.1
If the receiver serial lines are polarity reversed, the core might fail to link train in a Gen 2 slot.
Is there a fix for this?
This problem occurs only if all three of the following conditions are met:
1. Endpoint is plugged into a GEN 2 slot.
2. Any of the Endpoint lanes receiving serial lines is polarity reversed.
3. The motherboard is setting the Autonomous Change Bit in the TS1/TS2 ordered sets.
A fix for this issue is available in the v1.9 Rev 1 patch. See (Xilinx Answer 31572) for access to the patch.
01/07/2009 - Added Patch Availability.
09/10/2008 - Initial Release.