Why does the XPS UARTlite v1.00b not transmit any data during HDL simulation?
The status_reg signal in the uartlite_core.vhd is not properly initialized. To work around this problem and maintain the current hardware functionality, perform the following:
1. Open C:\Xilinx\10.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_uartlite_v1_00_a\hdl\vhdl\uartlite_core.vhd
2. Edit line 190 as follows:
from: signal status_Reg : std_logic_vector(0 to 7);
to: signal status_Reg : std_logic_vector(0 to 7) := (others => '0');
A new revision of this core is released in 11.1 which will fix the status_reg initialization problem.