We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Page Bookmarked

AR# 31660

10.1 ISE - Running "Simulate Post-Place & Route Model" process on SysGen design gives: "Unable to find <designname>/dut"


I have a System Generator design I would like to open in XPower using a Vector Change Dump (.vcd) file generated by ModelSim. However, when I try to produce the .vcd file from the ModelSim "Simulate Post-Place & Route Model" process, I receive the following error in ModelSim:

"Unable to find <designname>/dut"

# -- Loading entity <top module name>

# vsim -lib work -sdfmax /UUT=netgen/par/<top module name>_timesim.sdf -t 1ps <top module name>_tb

# ** Note: (vsim-3812) Design is being optimized...

# ** Error: (vopt-2216) Failed to find instance 'UUT' .

# ** Error: (vopt-1943) Command line SDF instance pathname "/UUT" cannot be resolved.

# Optimization failed

# Error loading design

# Error: Error loading design

# Pausing macro execution

# MACRO ./<top module name>_tb.tdo PAUSED at line 10


First, the post-route simulation flow for ModelSim generates an invalid UUT instance name in the tdo file "vcd add" command for the given testbench instance.

The second issue is that SysGen generates "Sysgen_dut" instance name in the pn_postpar.do which does not match the default UUT name for this property.


Add these two lines in the pn_postpar.do file just before 'run' :

vcd file outfile.vcd

vcd add <testname>/sysgen_dut/*

This problem has been fixed in the latest 10.1 Service Pack available at:


The first service pack containing the fix is 10.1 Service Pack 3.

AR# 31660
Date 05/13/2010
Status Archive
Type General Article