In some multi-lanes, Virtex-5 Aurora designs have been seen to have the data misaligned on what corresponds to a single lane. This might appear to the user application as data errors, as there is no method to determine that data is being received out of order. This Answer Record discusses the cause of this problem and provides patches for both Windows and Linux applications.
Some multi-lane applications of the Virtex-5 Aurora Core have been seen to have one or more lanes misaligned, causing what appears to be data errors at the user interface. To work around this problem, the following patches should be installed and the core regenerated:
To install either patch, extract the appropriate patch into the Xilinx install directory. This will be the same directory to which the XILINX environment variable points. Accept any prompts requesting to overwrite files. Once the patch is installed, the Virtex-5 Aurora Core will need to be re-generated and re-incorporated into the full design.