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AR# 31692

XtremeDSP Development Kit - Where can I find information about the Interrupts?


Where can I find information about the Interrupts?


Q1. What is the difference between the DMARead() and the DMAReadToLockedMem(), the FUSE C++ API documentation does not explain the difference?

A1. The DMAReadToLockedMem() is best used if you can lock memory down and reuse if for the data transfers. Effectively DMARead() just locks the memory and then calls DMAReadToLockedMem() and then unlocks the memory. The DMAReadToLockedMem() can be more efficient, but it does depend on where and how you store your data.

Q2. Does the FUSE Software install the actual Interrupt Service Routine (ISR) for the card so the user does not have to provide that?

A2. Yes the FUSE Software install provides the ISR.

Q3. What is the flow of events from ISR generation by the FPGA to detecting that the interrupt was generated by DIME_InterruptStatus?

A3. The user FPGA should generate a low pulse on its interrupt pin. The pulse should last for a few clock cycles as the PCI FPGA runs at 40 MHz and in general the user FPGA runs faster; therefore, the user needs to make sure the interrupt is held long enough for the PCI FPGA to latch this. When this pulse occurs, the PCI FPGA sets a bit in the interrupt status register and the interrupt line on the PCI bus is driven low. This causes the ISR in software to get called. The ISR reads the status register which clears the interrupt line and wakes up any waiting threads.

Q4. Also, in the Application Note "NT302-0000_Spartan_to_Virtex_Interface" the only documentation on the INT interrupt line is in the one liner in the signal descriptions table. Is this line an edge or level sensitive interrupt line?

A4. The Interrupt from the user FPGA is latched on the positive edge of the signal. Basically the sequence is that when there is a rising edge on the interrupt line from the User FPGA, the interface FPGA, latches this and puts out a level based interrupt to the PCI bus, which is then cleared when the appropriate register is read by the interrupt handler

Q5. How long do I have to assert it (INT='1') to generate an interrupt on the PC?

A5. The PCI FPGA runs at 40 MHz, so the INT should be asserted for at least 3 clock periods.

Q6. Does DIME_InterruptControl() with the dintWait poll if dintBLOCKING is not used? If so, what is it polling on?

A6. We currently only support dintBLOCKING for the dintWAIT command.

Q7. Are the any other examples for using interrupts with DMA?

A7. Unfortunately, we have no other information or examples than that provided on the CD or in the install area, for using the DMA interface with Interrupts.

For more information about FUSE differences in the APIs, see (Xilinx Answer 31062).

For more information about the DMA Interface and available information, see (Xilinx Answer 31534).

AR# 31692
Date 12/15/2012
Status Active
Type General Article
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