We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 31693

10.1.03 System Generator for DSP - Release Notes, README, and Known Issues List


Keywords: MATLAB, Simulink, errata, KI, SysGen, 10.1.03

This Answer Record contains the Release Notes and Known Issues for System Generator for DSP 10.1.03.


For System Generator for DSP Release Notes from other versions, see (Xilinx Answer 29595).

Release Notes and Known Issues in System Generator for DSP 10.1.03

System Generator for DSP 10.1.03 is a minor update. Please read the documentation, because it answers questions you might have about changes to the functionality or the look from previous versions of System Generator for DSP. The System Generator User Guide is accessible in PDF format at:

Software Support

- What software is required to install System Generator for DSP? See (Xilinx Answer 17966).

Xilinx DSP Blockset Enhancements
DSP48 Abstraction for Mathematical Operators
Accumulator, AddSub, and Counter blocks can now be implemented using either a DSP48 or the original LUT-based implementation. This enables design portability across all supported Xilinx devices.

Fast Fourier Transform 6.0
New block now available in System Generator with the following features:
- Extended data and phase factor width to 34 bits
- Block floating-point support available for Pipelined, Streaming I/O architecture

WaveScope waveforms can now be directly sent to a printer from WaveScope and a "Print Preview" capability allows you to view and customize the waveform formatting before printing. This capability can be accessed via the File pull-down menu or a toolbar shortcut.

Xilinx Block Set Issues

- Why does the DSP48 Opmode block have invalid characters reading "PCIN>>17" instead of "PCIN>>17"? See (Xilinx Answer 30790).
- Why does the post-MAP resource estimation return zero for all resources except IOBs? See (Xilinx Answer 30675).

General Issues

- Why does Simulink report that my output type is obsolete in MATLAB 2008a when I have a signal width greater than 54 bits? See (Xilinx Answer 31255).
- When using System Generator on a 64-bit XP machine, why do I receive a message stating, "There is a problem with your Xilinx ISE installation or with your Xilinx environment variable" and "could not run java.exe"? See (Xilinx Answer 29512).
- When trying to use System Generator on Windows Vista, why do I receive an error stating "gcc.exe: installation problem, cannot exec 'cc1': No such file or directory. Error occurred during Simulation Initialization"? See (Xilinx Answer 30977).
- Why do I see an instantiated register called "xlpersistentdff" in a System Generator for DSP design? See (Xilinx Answer 24257).
- JTAG Hardware Co-Sim with non-Xilinx parts in the chain causes error. See (Xilinx Answer 19599).
- Why do I receive "Error 0001: caught standard exception" error when using IBM Clear Case? See (Xilinx Answer 24263).
- Why do post-PAR simulation mismatches occur when running a design at faster than 200 MHz? See (Xilinx Answer 24268).
- I cannot generate an NGC, Bitstream, Timing Analysis, or Hardware in the Loop target when using Synplify as my synthesis tool. Why? See (Xilinx Answer 24273).
- Why are there simulation mismatches at the beginning of the HDL simulation generated from System Generator for DSP when Synplify is used for synthesis? See (Xilinx Answer 29170).
- Why does the design fail to generate when using a FIFO block, From FIFO block, or To FIFO block in the design, and the target path is more than 160 characters? See (Xilinx Answer 23614).
- Why do I receive the message "xledkpostgen>PLBPcoreBuilder at 234" when netlisting my EDK PCORE design from System Generator? See (Xilinx Answer 31068).
- Why do I receive "Error while executing C MEX S-function 'sysgen', (mdlTerminate). Unexpected unknown exception from MEX file" when I simulate my System Generator model? How do I set up my system environment properly? See (Xilinx Answer 31095).
- Why do I receive the message "Failed to execute command "project set {Synthesis Tool} {Synplify Pro (VHDL/Verilog)}"" when trying to use Synplify Pro for my synthesis tool form System Generator? See (Xilinx Answer 31112).
- During simulation of my FFT v5.0 design, why do I receive the error "FFT simulation did not complete successfully" when my FFT is configured for dynamic transform size? See (Xilinx Answer 31271).
- Why is my reset signal on my FIFO not behaving the same in hardware as it did in software? See (Xilinx Answer 31294).
- For a multi-channel implementation, why is the FIR Compiler Chan_In output offset by a clock cycle from the actual channel it is accepting? See (Xilinx Answer 31454).
- When I use the CIC Compiler filter with an input data rate less than the system clock rate controlled by ND, I see mismatches between the simulation results in System Generator versus hardware co-simulation. See (Xilinx Answer 31455).
- Why am I unable to see the expected behavior after recompiling my C-code for my EDK Processor block when my EDK project uses SDK for compilation? See (Xilinx Answer 31622).
- Why do I receive an error during synthesis stating "ERROR:HDLParsers:850 - Formal port "port name" does not exist in Component"? See (Xilinx Answer 31792).
- Why do I receive an error message stating "continuous sample times are not allowed" when driving a Simulink Spectrum Scope with Xilinx System Generator blocks? See (Xilinx Answer 31933)
- When running a MATLAB Student Edition, why do I receive the error message "Error evaluating 'OpenFcn' callback of Xilinx Gateway In Block block (mask)"? See (Xilinx Answer 31934).
- Why do I receive "Fatal Internal Error" when my design contains "inport" and "output" blocks at the top level of my Simulink model for Data Import/Export? See (Xilinx Answer 31935).
- When running MAP, why do I receive "ERROR:Place:673 - DSP component is the start of a cascate of DSP components"? See (Xilinx Answer 31937).
- When I run synthesis on my System Generator design, the following error occurs: "ERROR:XST:2587 - Port has different type". See (Xilinx Answer 31998).
- Why does my System Generator generated PCORE not work or hangs my processor when implemented in EDK? See (Xilinx Answer 32801).

AR# 31693
Date 06/01/2009
Status Active
Type General Article
Page Bookmarked