Occasionally, the testbench will timeout, or the design fails in timing simulation but passed in functional simulation. The design met timing, and there were no errors reported.
This is caused by a potential negative setup and hold issue described in (Xilinx Answer 30815). To work around this issue, change the MOST and OPB clocks to 30000 ps in the testbench.
This issue will be fixed in the 11.1i release.