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AR# 31778

10.1 EDK, PPC440MC_DDR2 - How do I use the PPC440MC_DDR2 memory controller and set MI_CONTROL?


How do I use and parameterize the PPC440MC_DDR2 Core? Are there any suggestions in its use? How do I set MI_CONTROL?


Below is a simple list of PPC440MC_DDR2 application information:


PPC440MC_DDR2 is only for Virtex-5 FXT using DDR2 memories; all other devices and memory types must use MPMC. PPC440MC_DDR2 is higher performance than MPMC for the PPC440 processor.

MHS Connectivity

To connect the PPC440MC_DDR2 to the PPC440, the use of the XPS Base System Builder (BSB) is recommended. Following is an example connection:

PPC440 Instance


PORT CPMMCCLK = sys_clk_s



PORT mc_mibclk = sys_clk_s

Pin-out and UCF Modification

Always try to use one of the UCFs in the pcore/data/ucfs directory for memory pin-out during board layout. The pin-out can be modified by following (Xilinx Answer 29313), with the requirement that static timing analysis passes with the new pin-out and UCF constraints. Also, if timing errors occur, consider setting the C_READ_DATA_PIPELINE parameter, which will increase latency, but will make it easier to meet timing. The predefined UCFs should have the fastest timing, however.

Changing Memory Part Information

Changing the DDR2 memory setup requires changing a few parameters, in addition to the usual memory data sheet timing parameters and port widths of the memory controller. Both the PPC440MC_DDR2 and PPC440 cores must be parameterized to reflect memory changes:

PPC440MC_DDR2 Instance


The C_DQS_IO_COL and C_DQ_IO_MS parameters must be changed as the DQ and DQS pin-outs change. These parameters are in the predefined UCFs and also in the PPC440MC data sheet. For custom pin-outs, see (Xilinx Answer 29313).

PPC440 Instance


These inform the PPC440 Memory Controller Interface (MCI) about how the memory addresses are broken up between rows and banks. It is just a simple indication of which address bits changes result in a change of a row, and which result in a change of a bank address. Note that the 4 LSBs are dropped when specifying the parameter, since the full address is 36 bits, but must fit into a 32-bit register.

Information on how to calculate these is found in the PPC440MC_DDR2 data sheet; search for these parameters. Reference the specific memory data sheet used to know the number of row, column, bank, and DQ bits per memory collection.


MI_CONTROL sets the PPC440 MCI to have the correct data widths, latency, and row/bank management behavior.

See "Embedded Processor Block in Virtex-5 FPGAs", embedproc_ug200.pdf, located in the EDK doc\ directory for individual bit settings. Suggested settings are as follows, by bit location:

[0] enable: '1'

[1] Rowconflictholdenable:'1'

[2] Bankconflictholdenable:'1'

[3] Directionconflictholdenable: '1'

[4:5] Autoholdduration: "10"

[6] 2:3 Clock Ration mode: Depends on clock setting, '0' if using an integer clock ratio of MCI to PPC440 Core

[7] overlaprdwr: '0'

[8:9] Burstwidth: Should be double the DDR memory DQ data width, since two DQ widths are transferred per memory clock period when using DDR2 memories, yet the MCI runs at SDR rate, but twice as wide. Valid SDR burst widths are: "00" (128-bit), "01" (64-bit), and "11" (32-bit).

[10:11] Burstlength: Must be half PPC440MC_DDR2 burstlength, C_DDR_BURST_LENGTH, since two DQ widths are transferred per clock cycle. Thus "01" (2) for C_DDR_BURST_LENGTHs of 4 and "10"(4) for a C_DDR_BURST_LENGTH of 8.

[12:15] Write Data Delay (WDD): "0000"

[16] RMW: '1' if using ECC, '0' otherwise. Same as C_INCLUDE_ECC_SUPPORT on PPC440MC_DDR2 instance. See PPC440MC_DDR2 data sheet for restrictions.

[17:23] Reserved: "0000000"

[24] PLB Priority Enable: Either '0' or '1', '1' is chosen by BSB.

[25:27] Reserved: "000"

[28] Pipelined Read Enable: '1'

[29] Pipelined Write Enable: '1'

[30:31] Reserved: "11"

AR# 31778
Date 12/15/2012
Status Active
Type General Article
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