After generating my System Generator netlist, I receive the following error during synthesis:
ERROR:HDLParsers:850 - "file name" Line ###. Formal port RDY does not exist in Component 'cic_compiler_virtex5_1_2_b11e4f92639243a0'.
This can occur because of a known issue where two identical instances of a System Generator block are used in a model with slightly different ports used on each instance. The problem occurs because of the component port list does not look at the ports used on all instances of the block.
To work around this issue, wire all the outputs of those blocks to some logic in your design. This can be dummy logic, such as a dangling register, which will be optimized out and hence use no additional hardware inside the final FPGA design.
This issue will be resolved in a future release.